The present invention relates generally to personal computers and in particular to memory buses in personal computers.
Personal computers, as shown in FIGS. 1A and 1B, include a monitor 100, keyboard input 102 and a central processing unit 104. The processor unit typically includes a microprocessor 106, a memory bus circuit 108, and other peripheral circuitry 110. The memory bus is provided with a number of expansion sockets to allow the purchaser of the personal computer to install additional memory circuits as the user""s needs change. A number of expansion sockets for memory upgrades typically exist along a memory bus. The expansion sockets remain empty unless the user decides to upgrade the system""s memory by installing additional memory circuits. However, users frequently do not fill the expansion sockets, resulting in a memory bus that is operating under a less than maximum load.
In general, the characteristic impedance of the computer""s memory bus interface is designed to match the impedance of a fully loaded memory bus. Thus, when the memory bus is fully loaded, the interface and the bus are matched. However, when the memory bus is minimally loaded, the mismatch in impedance creates a ringing effect on the bus which results in overshoot and undershoot in a signal communicated over the bus. The ringing is a result of signal xe2x80x9cghostsxe2x80x9d which reflect or bounce along the communication line. As memory bus communication speeds increase, the ringing effect is more likely to result in communication errors. Although termination devices can be installed on the bus to alleviate some of the ringing, the current designs require the end user to properly relocate the termination device on the bus when installing additional memory. Installing the termination device in the wrong socket can worsen the ringing effect.
Another approach to solving the problem of mismatched impedances is to design a high-speed memory bus optimized for both minimum and maximum loading conditions. Such a design task increases in difficulty as the speed of the bus increases. Obviously, bus design can be simplified if the difference between the minimum and maximum loading conditions is small.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a computer which combines expandable memory with a high speed communication bus without incurring data errors due to impedance mismatch when the computer operates with less than the full compliment of memory.
The above mentioned problems with communicating with high speed memories and other problems are addressed by the present invention and which will be understood by reading and studying the following specification.
In particular, the present invention is a memory bus impedance matching module with a module housing adapted to fit into a memory socket of a memory bus. The module housing has locations for N number of impedance devices and includes communication line connections. N impedance devices are mounted on the housing and coupled to the communication line connections. Each memory bus impedance matching module exhibits an impedance substantially equal to that of a functional memory module adapted to fit into the memory expansion socket. The module housing can be manufactured to fit into a socket designed to receive a JEDEC standard circuit package, such as a single or dual in-line memory module. The impedance devices are defective packaged direct random access memory (DRAM), DRAM dies, or other devices exhibiting an impedance substantially similar to a functional memory device. The memory bus impedance matching module can be powered to more closely match the impedance of a functional memory module.
In another aspect of the invention, a memory bus comprises a functional memory module and a memory bus impedance matching module. The memory bus impedance matching module is populated only with impedance devices and exhibits substantially the same impedance as the functional memory modules. The memory bus impedance matching module also comprises communication line connections suitable for coupling to the memory bus and which are coupled to the impedance devices.
In yet another aspect of the invention, a method is described that reduces errors in a memory bus connected to a microprocessor when at least one expansion socket on the memory bus is empty and one functional memory module is coupled to the bus. The method comprises the step of installing a memory bus impedance matching module in each empty socket on the memory bus. The memory bus impedance matching module is populated only with impedance devices and has an impedance substantially equal to that of the functional memory module. The method optionally includes the step of replacing a memory bus impedance matching module with a functional memory module.
A method of making the memory bus impedance matching module is also disclosed.
Because the memory bus impedance matching module exhibits the same load as a functional memory module, the impedance of the memory bus remains constant regardless of the amount of real memory installed in the computer system and communication errors are reduced. System architecture design is simplified as the designer need only be concerned with optimizing memory bus operations under fully loaded conditions. Further, upgrading of memory by the end-user is made easier than with the prior art termination devices since the end-user merely replaces a memory bus impedance matching module with a functional memory module without the inconvenience of relocating the termination device.